Substrates of electronic assemblies are made of a variety of materials that are subject to shrinkage, when the substrates are cured. For example, the green tape for low-temperature co-fired ceramic (LTCC) substrates shrinks upon firing, which can result in difficulty in precisely locating solder pads for proper printing of flux and solder on the solder pads. Furthermore, solder/flux stencil design has not taken into account the variation in substrate shrinkage across the substrate and within specific regions of the substrate. In general, the amount of substrate shrinkage has been predicted from an expected shrinkage, based on materials used and the process steps implemented.
In a typical case, substrate shrinkage can result in a plus or minus 0.4 percent uncertainty, e.g., about twenty mils over a five inch substrate, in the location of a particular solder pad. On circuits built on larger substrate panels, e.g., six inch by six inch panels, the shrinkage of the substrate material may result in unacceptable product builds. This is especially true where large panels are structured in an array-type format. In general, current substrate shrinkage compensation techniques utilize post-firing substrate measurements to correct an initial 1:1 artwork used to create a solder stencil. In this manner, the overall solder stencil artwork is corrected for the substrate shrinkage globally. However, the solder stencil artwork is not corrected for non-uniform shrinkage, which may be caused by a metallization difference, across the substrate.
With reference to FIG. 1, a relevant portion of a prior art substrate 10 is depicted that includes a plurality of conductive traces 12 that are coupled to solder pads 14 and 16. As is shown in FIG. 1, solder 14A has been misprinted such that it is only partially located on the pads 14. Similarly, solder 16A has been misprinted such that it only partially touches the solder pad 16. While such misregistered solder prints may provide a functional electronic assembly, depending upon the type of electronic components utilized in the assembly, a misaligned solder stencil may cause an electronic assembly that utilizes fine lead pitch electronic components, e.g., components having a pitch of about twenty mils or less, to be defective.
What is needed is a technique for compensating for substrate shrinkage during manufacture of an electronic assembly that prevents improper solder placement.